ARM Cortex M3 - advanced embedded C programming with CMSIS standard libraries

Overview
It is a 5 days hands on course that will review the Cortex M3 architecture from the perspective of the embedded systems application developer and the various peripheral combinations to be found on ARM Cortex M3 based micro-controllers and how the need for portability has led to the development of a standard API for programming the various peripherals. The course assumes that attendees are, by and large, familiar with the various protocols underlying the common peripherals. The relevant protocols will be described briefly, but there will not be time to go into any of them in great depth. Rather the course will proceed via a collection of case studies and exercises aimed at making the best use of the available CMSIS libraries for the target processors used on the course. These will be higher end STM and LPC Cortex 3M processors. The course will also consider how the CMSIS libraries can be used either stand alone, or, in conjunction with a small embedded RTOS such as PowerPac.
Note: this course can be tailored to specific micro-controllers and specific subsets of CMSIS if required. Please contact FTT for further details.
This is a taught course with labs, with a split of about 60% teaching and 40% labs.

Course Benefits
On completion of the course attendees will understand

• how the various on chip and off chip peripherals are attached to the Cortex M3 core
• interrupt configuration and memory configuration in C
• the process of configuring and driving a wide range of peripherals using the CMSIS library APIs for these peripherals
• how to use the CMSIS library together with an embedded RTOS
• implementing interrupt and exception handlers in C
• memory maps, memory protection unit, and priviledged operation
• implementing device drivers for both on chip and off chip peripherals, and making use of Direct Memory Access (DMA)

Course Contents
Overview of the CMSIS Standard

• Rationale for developing the CMSIS standard
• The layered architecture underlying the CMSIS standard
• Layers supplied/specified by ARM
• Core Peripheral Access Layer
• Middleware Access Layer
• Components of the standard
• specifications for functionality for accessing peripheral registers and defining exception vectors
• specifications for naming register names of the core peripherals and the core exception vectors
• specification of a device independent interface for RTOS Kernels including a debug channel
• specification of interfaces for middleware components (TCP/IP Stack, Flash File System)
• Functionality added by ARM's Silicon partners
• device peripheral access layer functionality
• Helper access functions for peripherals

Survey of particular implementations of the CMSIS standard

• STM32 CMSIS implementation
• LPC CMSIS implementation

Examples and Case Studies of Working with CMSIS

• GPIO - button presses and LED flashing ( polling, interrupt and timer driven variations )
• RS232 - Polling oriented USART application
• RS232 - Interrupt driven UART I/O application development
• A/D and D/A
• Watchdog
• Nesting Interrupt Functions
• PWM
• Realtime clock
• SVC - Software Interrupts
• Tamper
• USB - HID example
• USB - Mass storage example
• Memory allocation
• Interfacing with a small RTOS (Powerpac)
• Debugging CMSIS based applications