Introductory digital systems laboratory

Lectures: 3 sessions / week, 1 hour / session

Recitations: 1 session / week, 1 hour / session

Labs: Open hours for the entire semester

Katz, Randy, and Gaetano Borriello. Contemporary Logic Design. 2nd ed. Upper Saddle River, NJ: Prentice Hall, 2004. ISBN: 9780201308570.

There are plenty of good Verilog® books and online resources. We recommend the following book for a basic introduction to Verilog®:

Palnitkar, Samir. Verilog® HDL. 2nd ed. Upper Saddle River, NJ: Prentice Hall, 2003. ISBN: 9780130449115.

Pinouts for most components are easily available through the Web (e.g., do a Google™ search to locate the appropriate data sheet). Relevant sheets needed for the labs are available in labs section.

In the first couple of weeks of the term, there will be lectures on Friday (to quickly ramp up on material needed for lab 1). Then, Fridays will be used for recitations (three parallel recitation sections). Lectures and recitations are discontinued at the end of the term so you can focus on the final project (see course schedule for details). We will meet in the lecture hall for project group presentations after the block diagram conferences.

All laboratory exercises must be completed; these are intended to prepare you for the term project. In doing these exercises, each student works individually. We strongly recommend that you use a computer-based drawing package to draw block diagrams and schematics for the lab reports and final project.

Three problem sets will be issued. The problem sets will emphasize the material covered in lectures and recitations and the primary goal is to help you prepare for the labs.

There will be one quiz during the term before Drop Date.

The most important assignment is the Term Project, about which you will receive more detailed instruction later. In doing this assignment, you will work with one or, at most, two partners. You should begin finding your partner(s) early in the term.

The Lab 1 checkoff sheet is to be initialed by a TA or LA and included with your report. Note that the checkoff sheet is not the report. Lab 1 report template is available in the labs section.

Lab 2 report will be used for part of the CIM requirement. More details will be provided in lecture.

Lab 3 will only include the checkoff. There is no need to write a detailed lab report for lab 3. The lab will have instructions on what is to be turned in.

Lab 4 has an intermediate checkoff (not graded) and the final checkoff. There is virtually no modification required to a report depending on the working of your lab implementation. However, reports with no lab effort will receive a zero.

The term project requirements must be completed in accordance with the schedule given in the instructions. You must make a presentation of your part of your project to the rest of the class after the logic diagram conference. You must demonstrate (i.e., present) your term project even if it does not fully function, and you must submit the written report in order to receive a passing grade.

An approximate breakdown for final grades is as follows:

Late work will be penalized. Lateness of the lab assignments will result in a 20% per day penalty for work completed 1-5 working days after the due date. No point credit will be given for unexcused lateness exceeding 5 days. The final project must be done on time.

You may discuss labs with anyone (staff, former students, other students, etc.), but then do the work on them individually. Do not copy anything, including computer files, from anyone else.

Collaboration with your partners on the project is desirable. Project reports should be joint with individual authors specified for each section. You may copy anything you want, with appropriate attribution, for your project report.

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