Advanced VHDL for Design

Introduction, Recap of Design Units, Latest VHDL Standards, The RTL Synthesis Subset, Books and Other Resources, The ASIC Design Flow, VHDL in the Design Flow, Effects of Coding Style on Synthesis Results, Coding Style and Synthesis Runtime, Type Guidelines, Types and Subtypes, Recommended Types for Synthesis, Preparing for Reuse, Advantages of reuse, Designing Reusable IP, Managing VHDL Libraries, Limitations of Standard Approach, Recommended Library Structure, Exploiting Entities and Architectures, Advantages of Multiple Architectures, Synthesis Considerations, Using Subprograms Efficiently, Synthesis Limitations, VHDL Configurations, The Power of Configurations, What Works with Synthesis, Opeimising for Power, Optimising for Area, Optimising for Speed