ARM Cortex M3 - architecture and assembly lanaguage programming

Overview
It is a 5 days hands on course that will cover the Cortex M3 architecture from the perspective of the embedded systems application developer. The instruction set of ARM Cortex processors will be covered with practical examples. Knowledge of the architecture and instruction set and of techniques for writing efficient and well structured assembler will be of particular use to those developing low level device drivers, firmware and implementing or porting existing embedded operating systems to the architecture. This knowledge will also be needed by those maintaining libraries coded in optimised assembler such as signal processing libraries or maths libraries.
This is a taught course with labs, with a split of about 60% teaching and 40% labs.
The course will use an STM32 target board and IAR's EWARM IDE for assembly language programming, simulation and debugging.
Note: This course can be tailored to use other target boards. Contact FTT for further details.

Course Benefits
On completion of the course attendees will understand

• The embedded systems design and application requirements that influenced the design of the ARM Cortex architecture and its instruction set
• the Thumb 2 instruction set
• structured assembly language programming techniques
• ARM Cortex memory systems
• exceptions and interrupts and their handling
• memory maps, memory protection unit, and priviledged operation
• implementing device drivers for both on chip and off chip peripherals, and making use of Direct Memory Access (DMA)

Course Contents
Overview of the ARM Cortex-M3 processor

• Evolution of ARM architectures
• Micro-controller features for C compiler and embedded system friendly designs
• Cortex M3 architecture features
• Cortex M3 Registers
• Operation modes
• Nested Vectored Interrupt Controller
• Memory map
• Bus interface
• Memory protection unit
• Instruction set
• Built in debugging support
• Low power consumption support

Memory Systems and the Cortex M3

• Memory maps
• Access control attributes and default access permissions
• Bit band operations
• aligned vs. unaligend transfer
• exclusive access and semaphore implementation
• endian mode and SoC issues
• instruction set support for converting between big endian and little endian

Exceptions and Interrupts

• Exception types
• Exception priorities
• Interrupt Vector tables and Vector table relocations
• IRQ inputs and pending behaviour
• Fault Exceptions
• Interrupt Configuration
• Interrupt enable and Clear enable
• Interrupt pending and Clear pending
• Priority levels
• Active Status bits
• PRIMASK and FAULTMASK special registers
• BASEPRI special register
• The System Handler and Control State Register
• Code patterns and templates for setting up interrupts
• Software interrupts
• SYSTICK timer - configuration, usage and control
• Interrupt behaviour patterns
• vector fetches
• register updates
• exception exits
• interrupt nesting
• interrupt tail-chaining
• interrupt latency
• interrupt related faults
• stacking
• unstacking
• bus or memory management faults during a vector fetch
• invalid returns

Assembly language programming examples and case studies

• GPIO pins and their configuration
• lighting an LED - the "Hello World of Embedded Programming"
• Flashing an LED using software delays
• Detecting a button press by polling
• Detecting a button press via an external interrupt
• Flashing an LED using a timer and polling
• Flashing an LED using a timer and timer interrupt handling
• Storing text data in data memory
• Programming UARTs and RS232 communication with a PC
• Implementing Semaphores using Exclusive Access
• Implementing Semaphores using Bit-Band
• Constructing Decision Trees using Bit Field Extract (UBFX) and Table Branch(TBB) Instructions
• Setting up Vector Tables and Interrupt Priorities
• Working with software interrupts
• passing a parameter in the context of an SVC call
• using an SVC for accessing output functions
• implementing a system with two separate stacks
• use and setup of the Memory Protection Unit (MPU)
• use and setup of the SYSTICK timer

Understanding the Cortex Debug Architecture

• Overview
• Debug modes
• Debug events
• Breakpoints in the Cortex-M3
• Accessing register content in Debug mode
• Cortex M3 dbugging components - an overview
• Practical debugging using EWARM IDE