Introduction to Verilog
Training
Blended learning in Dalmine (Italy)
*Indicative price
Original amount in EUR:
1,500 €
Description
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Type
Training
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Level
Advanced
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Methodology
Blended
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Location
Dalmine (Italy)
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Class hours
24h
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Duration
Flexible
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Start date
Different dates available
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Delivery of study materials
Yes
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Personal tutor
Yes
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Virtual classes
Yes
A 3 day course teaching designers to write efficient, accurate RTL code for synthesis as well as basic testbenching and verification techniques. This course is intended for designers who are new to Verilog and who wish to become familiar with the language with a particular emphasis on writing RTL code for synthesis. We also cover how to construct testbenches for unit level verification of your RTL code. This course continuously mixes lecture and exercise. There is a simulation exercise for most topics providing a very hands-on experience. Synthesizable constructs are clearly identified and appropriate synthesis coding techniques discussed.
Facilities
Location
Start date
Start date
Start date
About this course
Design engineers wishing to adopt the Verilog language for digital design and basic functional verification.
Basic knowledge of digital design is essential, experience with a programming language is beneficial.
Attendance Certificate
An introductory course which assumes no prior knowledge of Verilog and teaches the skills required to write efficient code
Reviews
Subjects
- Verilog
- Testbench
- Hardware Design Language
- HDL
- RTL
- Design
- Web Development
- Web Programming
- Computer Programming
- Computer Architecture
Teachers and trainers (1)
Nigel Woolaway
Engineer
Course programme
Introduction to Verilog
*Indicative price
Original amount in EUR:
1,500 €